As is known in the art, one way to compensate for delays in passing data from a source (i.e., a source domain) to a plurality of different destinations (i.e., a destination domain) is to provide a flip-flop between the source domain and the destination domain. The flip-flop stores the data from the source domain and thus provides a data buffer. This buffered data is then available at a common time for each one of the different destinations, (i.e., the destination domain).
As is also known in the art, there is metastability in a flip-flop. To compensate for such metastability a design frequently includes a second flip-flop preceding the buffering flip-flop. Thus, a two flip-flop synchronizer is provided. This two flip-flop synchronizer approach allows for an entire clock period (except for the setup time of the second flip-flop) for metastable events in the first synchronizing flip-flop to resolve them before being latched in the second flip-flop.
As is also known in the art, it is frequently required that data processed in a first, or source domain, operating with one clock, be passed to a second, or destination; domain operating with a different, clock asynchronous with the first cloak, i.e., the two domains operate asynchronously.
As is also known in the art, prior to finalizing any design, the design is typically simulated. The inventors have recognized that with such an asynchronous system, there is a randomness of the arrival of the valid and stable signal in the destination domain that is not accounted for during the initial design simulation phase. That is, the inventors have recognized that it could take (one or two) clocks under one placement and routing condition or (two or three) clocks under a different placement and routing condition for the valid signal to arrive at the receiving block because of the relative phase between the clock operating the source domain and the clock operating the destination domain. This randomness is due to the possibility of the first stage of the two stage synchronizer of going meta-stable which occurs when a signal misses the required setup time of the synchronizer flip flop and of the fact that synthesis placement and routing of signals crossing clock domains are usually constrained in static timing as a multi-cycle path. Current verification approach of dealing with this issue has been to lock the arrival delay of the synchronized signal to two clocks (i.e., assume that the first stage flip flop never goes meta-stable) and perform verification based on that assumption. This approach could open up the possibility of masking a functional bug in the receive logic if it happens that the arrival time of the synchronized signal matter to that logic. i.e., if the destination domain would behave differently if the cross clock domain signal arrives two clocks delayed verses three clock delayed.
More particularly, traditionally, designers infer for the simulation, two back-to-back flip flops “synchronizers” in the register transfer level (RTL) “verilog” code to insure stable transition of signals crossing clock boundaries. This in turn fixes the delay in between the clock domains into two clocks, thus implicitly assuming that the first synchronization stage never goes meta-stable. Functional simulation of logic in the domains, normally progresses on this assumption. In reality, the first synchronizer stage would and could get meta-stable (this is the purpose of the meta-stable flip flops to begin with) and thus delay the arrival of the valid and stable signal by an extra clock cycle. The inventors have recognized this as a random event that could be affected by the phase alignment of the launch and receive clocks and have accounted for it in accordance with the present invention.
More particularly, the inventors discovered that in order to accurately simulate the behavior of signals crossing clock boundaries, it is essential to model the random behavior of the meta-stability phenomena encountered in such scenarios. Therefore, it is important to have a meta-stable logical block that has the capability of varying the cross clock domain delay by either one clock cycle, by two clock cycles, or randomly selecting between the two.
The random selection of the delay (1 or 2 clock cycles) insures covering the various state cases and transitions of the receive logic, by exposing any functional dependencies on the arrival of cross clock domain signals. This would cover any functional anomalies simulating at the register transfer level (RTL) level.
The inventors have also recognized that a second condition exists because of the fact that ASICs and modem FPGAs are running at faster and faster speeds which should be accounted for in the design simulation. That is, any path that crosses clock boundaries most likely does not consist of single cycle timing in regards to static timing analysis or synthesis, also referred to as multi-cycle path. This could cause the actual time to register through the back-to-back flip-flops to actually be either two clock cycles or three clock cycles. Thus it is important to randomly select the delay (2 or 3 clock cycles) as well.
In accordance with the present invention, a simulation is provided that considers both conditions into consideration; i.e., a 1 or 2 clock cycles delay as well as a 2 or 3 clock cycles delay. Since the synthesis, placement, and routing of the networks crossing clock domains determine which one of the two conditions exist, using a single condition of 1, 2, or 3 clock cycles is not valid since it would over-test the design. A single condition can be made of randomly selecting (1, 2, or 3 clock cycles) and never transitioning from (1 to 3 clock cycles) or from (3 to 1 clock cycles). This will then take into consideration the meta-stability nature of the double flip-flops as well as the single and multi-cycle paths of signals crossing clock domains.
In accordance with the present invention, a simulation model for a system wherein data passes from a source domain to a destination domain, such source and destination domains operating with different, asynchronous clocks provided to the source and destination domains. The model includes a three-stage delay network fed by data from the source domain in response to clock provided to operate the source domain. The network operates in response to clocks provided to operate the destination domain. The model includes a selector having inputs fed by outputs of the three delays and an output fed to the destination domain, such selector randomly providing to the output of such selector outputs of the each of the delays from the three stage delay network.
In one embodiment, the selector output is randomly chosen only when the data in the source domain changes logical state from a logic low to high or from a logic high to low. Otherwise, if this were performed on every clock of the destination domain, the randomness would not be evenly distributed between all three-delay stages.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.